Sunday, September 20, 2015

Forth on RISC architectures

Here's an article about writing a Forth compiler for RISC architectures - which turns out to be harder than you'd think, given the simplicity of Forth.
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1 comment:

  1. Samuel A. Falvo IIMarch 19, 2016 at 4:34 PM

    Here's an up to date URL for the article listed above: http://kestrelcomputer.github.io/kestrel/2015/09/15/bspl-compiler

    The source of the complexity is that RISC is literally *too* simple for Forth. CISC and accumulator architecture machines often have instructions which are favorable to Forth-style stack management. RISCs rarely have hardware managed stacks, so have to be done in software, which robs both performance and memory compactness. To regain both, you need more sophisticated code generators, rivalling those found in C compilers.

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